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pfowler |
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/*************************************************************************
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Updated UART library (this one) by Andy Gock
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https://github.com/andygock/avr-uart
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Based on updated UART library (this one) by Tim Sharpe
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http://beaststwo.org/avr-uart/index.shtml
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Based on original library by Peter Fluery
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http://homepage.hispeed.ch/peterfleury/avr-software.html
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*************************************************************************/
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/*************************************************************************
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Title: Interrupt UART library with receive/transmit circular buffers
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Author: Peter Fleury <pfleury@gmx.ch> http://jump.to/fleury
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Software: AVR-GCC 4.1, AVR Libc 1.4.6 or higher
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Hardware: any AVR with built-in UART,
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License: GNU General Public License
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DESCRIPTION:
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An interrupt is generated when the UART has finished transmitting or
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receiving a byte. The interrupt handling routines use circular buffers
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for buffering received and transmitted data.
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The UART_RX_BUFFERn_SIZE and UART_TX_BUFFERn_SIZE variables define
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the buffer size in bytes. Note that these variables must be a
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power of 2.
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USAGE:
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Refer to the header file uart.h for a description of the routines.
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See also example test_uart.c.
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NOTES:
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Based on original library by Peter Fluery, Tim Sharpe, Nicholas Zambetti.
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Based on Atmel Application Note AVR306
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LICENSE:
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Copyright (C) 2012 Andy Gock
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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LICENSE:
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Copyright (C) 2006 Peter Fleury
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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*************************************************************************/
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/************************************************************************
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uart_available, uart_flush, uart1_available, and uart1_flush functions
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were adapted from the Arduino HardwareSerial.h library by Tim Sharpe on
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11 Jan 2009. The license info for HardwareSerial.h is as follows:
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HardwareSerial.cpp - Hardware serial library for Wiring
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Copyright (c) 2006 Nicholas Zambetti. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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Modified 23 November 2006 by David A. Mellis
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************************************************************************/
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/************************************************************************
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Changelog for modifications made by Tim Sharpe, starting with the current
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library version on his Web site as of 05/01/2009.
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Date Description
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=========================================================================
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05/11/2009 Changed all existing UARTx_RECEIVE_INTERRUPT and UARTx_TRANSMIT_INTERRUPT
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macros to use the "_vect" format introduced in AVR-Libc
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v1.4.0. Had to split the 3290 and 6490 out of their existing
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macro due to an inconsistency in the UART0_RECEIVE_INTERRUPT
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vector name (seems like a typo: USART_RX_vect for the 3290/6490
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vice USART0_RX_vect for the others in the macro).
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Verified all existing macro register names against the device
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header files in AVR-Libc v1.6.6 to catch any inconsistencies.
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05/12/2009 Added support for 48P, 88P, 168P, and 328P by adding them to the
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existing 48/88/168 macro.
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Added Arduino-style available() and flush() functions for both
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supported UARTs. Really wanted to keep them out of the library, so
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that it would be as close as possible to Peter Fleury's original
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library, but has scoping issues accessing internal variables from
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another program. Go C!
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05/13/2009 Changed Interrupt Service Routine label from the old "SIGNAL" to
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the "ISR" format introduced in AVR-Libc v1.4.0.
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************************************************************************/
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/************************************************************************
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Changelog for modifications made by Andy Gock, starting with the current
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library version by Tim Sharpe as of 05/13/2009.
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Date Description
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=========================================================================
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2013-05-19
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- You can now use ring buffers over 256 bytes in size
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- Used "uint16_t" instead of "unsigned int" etc
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2012-09-06
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- Added peek functions
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- Updated URLs in source and README
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- Cleaned up some indenting to be more readable
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- Changed uart_functions() to uart0_functions
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- Added macros to allow legacy naming
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2012-03-01
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- Fixed errors in ISR vector names for various devices
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- Added USART2 and USART3 support to those devices with 4x USARTS.
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- Selective enabling of USART0,1,2,3 as required. (set in uart.h)
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************************************************************************/
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <avr/pgmspace.h>
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#include "uart.h"
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/*
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* constants and macros
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*/
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/* size of RX/TX buffers */
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#define UART_RX0_BUFFER_MASK ( UART_RX0_BUFFER_SIZE - 1)
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#define UART_RX1_BUFFER_MASK ( UART_RX1_BUFFER_SIZE - 1)
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#define UART_RX2_BUFFER_MASK ( UART_RX2_BUFFER_SIZE - 1)
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#define UART_RX3_BUFFER_MASK ( UART_RX3_BUFFER_SIZE - 1)
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#define UART_TX0_BUFFER_MASK ( UART_TX0_BUFFER_SIZE - 1)
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#define UART_TX1_BUFFER_MASK ( UART_TX1_BUFFER_SIZE - 1)
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#define UART_TX2_BUFFER_MASK ( UART_TX2_BUFFER_SIZE - 1)
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#define UART_TX3_BUFFER_MASK ( UART_TX3_BUFFER_SIZE - 1)
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#if ( UART_RX0_BUFFER_SIZE & UART_RX0_BUFFER_MASK )
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#error RX0 buffer size is not a power of 2
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#endif
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#if ( UART_TX0_BUFFER_SIZE & UART_TX0_BUFFER_MASK )
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#error TX0 buffer size is not a power of 2
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#endif
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#if ( UART_RX1_BUFFER_SIZE & UART_RX1_BUFFER_MASK )
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#error RX1 buffer size is not a power of 2
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#endif
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#if ( UART_TX1_BUFFER_SIZE & UART_TX1_BUFFER_MASK )
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#error TX1 buffer size is not a power of 2
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#endif
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#if ( UART_RX2_BUFFER_SIZE & UART_RX2_BUFFER_MASK )
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#error RX2 buffer size is not a power of 2
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#endif
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#if ( UART_TX2_BUFFER_SIZE & UART_TX2_BUFFER_MASK )
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#error TX2 buffer size is not a power of 2
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#endif
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#if ( UART_RX3_BUFFER_SIZE & UART_RX3_BUFFER_MASK )
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#error RX3 buffer size is not a power of 2
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#endif
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#if ( UART_TX3_BUFFER_SIZE & UART_TX3_BUFFER_MASK )
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#error TX3 buffer size is not a power of 2
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#endif
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#if defined(__AVR_AT90S2313__) \
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|| defined(__AVR_AT90S4414__) || defined(__AVR_AT90S4434__) \
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|| defined(__AVR_AT90S8515__) || defined(__AVR_AT90S8535__) \
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|| defined(__AVR_ATmega103__)
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/* old AVR classic or ATmega103 with one UART */
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#define AT90_UART
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#define UART0_RECEIVE_INTERRUPT UART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect
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#define UART0_STATUS USR
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#define UART0_CONTROL UCR
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#elif defined(__AVR_AT90S2333__) || defined(__AVR_AT90S4433__)
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/* old AVR classic with one UART */
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#define AT90_UART
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#define UART0_RECEIVE_INTERRUPT UART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega16__) || defined(__AVR_ATmega32__) \
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|| defined(__AVR_ATmega323__)
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/* ATmega with one USART */
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#define ATMEGA_USART
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#define UART0_RECEIVE_INTERRUPT USART_RXC_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#elif defined(__AVR_ATmega8U2__) || defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega16U4__) || \
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defined(__AVR_ATmega32U2__) || defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U6__)
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/* ATmega with one USART, but is called USART1 (untested) */
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#define ATMEGA_USART1
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#define UART1_RECEIVE_INTERRUPT USART1_RX_vect
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#define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect
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#define UART1_STATUS UCSR1A
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#define UART1_CONTROL UCSR1B
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#define UART1_DATA UDR1
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#define UART1_UDRIE UDRIE1
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#elif defined(__AVR_ATmega8515__) || defined(__AVR_ATmega8535__)
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/* ATmega with one USART */
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#define ATMEGA_USART
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#define UART0_RECEIVE_INTERRUPT USART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#elif defined(__AVR_ATmega163__)
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/* ATmega163 with one UART */
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#define ATMEGA_UART
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#define UART0_RECEIVE_INTERRUPT UART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#elif defined(__AVR_ATmega162__)
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/* ATmega with two USART */
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#define ATMEGA_USART0
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#define ATMEGA_USART1
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#define UART0_RECEIVE_INTERRUPT USART0_RXC_vect
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#define UART1_RECEIVE_INTERRUPT USART1_RXC_vect
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#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
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#define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect
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#define UART0_STATUS UCSR0A
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#define UART0_CONTROL UCSR0B
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#define UART0_DATA UDR0
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#define UART0_UDRIE UDRIE0
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#define UART1_STATUS UCSR1A
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#define UART1_CONTROL UCSR1B
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#define UART1_DATA UDR1
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#define UART1_UDRIE UDRIE1
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#elif defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
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/* ATmega with two USART */
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#define ATMEGA_USART0
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#define ATMEGA_USART1
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#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
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#define UART1_RECEIVE_INTERRUPT USART1_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
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#define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect
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#define UART0_STATUS UCSR0A
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#define UART0_CONTROL UCSR0B
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#define UART0_DATA UDR0
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#define UART0_UDRIE UDRIE0
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#define UART1_STATUS UCSR1A
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#define UART1_CONTROL UCSR1B
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#define UART1_DATA UDR1
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#define UART1_UDRIE UDRIE1
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#elif defined(__AVR_ATmega161__)
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/* ATmega with UART */
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#error "AVR ATmega161 currently not supported by this libaray !"
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#elif defined(__AVR_ATmega169__)
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/* ATmega with one USART */
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#define ATMEGA_USART
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#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#elif defined(__AVR_ATmega48__) ||defined(__AVR_ATmega88__) || defined(__AVR_ATmega168__) || \
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defined(__AVR_ATmega48P__) ||defined(__AVR_ATmega88P__) || defined(__AVR_ATmega168P__) || \
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defined(__AVR_ATmega328P__)
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/* TLS-Added 48P/88P/168P/328P */
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/* ATmega with one USART */
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#define ATMEGA_USART0
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#define UART0_RECEIVE_INTERRUPT USART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSR0A
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#define UART0_CONTROL UCSR0B
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#define UART0_DATA UDR0
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#define UART0_UDRIE UDRIE0
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#elif defined(__AVR_ATtiny2313__)
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#define ATMEGA_USART
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#define UART0_RECEIVE_INTERRUPT USART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#elif defined(__AVR_ATmega329__) ||\
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defined(__AVR_ATmega649__) ||\
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313 |
defined(__AVR_ATmega325__) ||defined(__AVR_ATmega3250__) ||\
|
|
|
314 |
defined(__AVR_ATmega645__) ||defined(__AVR_ATmega6450__)
|
|
|
315 |
/* ATmega with one USART */
|
|
|
316 |
#define ATMEGA_USART0
|
|
|
317 |
#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
|
|
|
318 |
#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
|
|
|
319 |
#define UART0_STATUS UCSR0A
|
|
|
320 |
#define UART0_CONTROL UCSR0B
|
|
|
321 |
#define UART0_DATA UDR0
|
|
|
322 |
#define UART0_UDRIE UDRIE0
|
|
|
323 |
#elif defined(__AVR_ATmega3290__) ||\
|
|
|
324 |
defined(__AVR_ATmega6490__)
|
|
|
325 |
/* TLS-Separated these two from the previous group because of inconsistency in the USART_RX */
|
|
|
326 |
/* ATmega with one USART */
|
|
|
327 |
#define ATMEGA_USART0
|
|
|
328 |
#define UART0_RECEIVE_INTERRUPT USART_RX_vect
|
|
|
329 |
#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
|
|
|
330 |
#define UART0_STATUS UCSR0A
|
|
|
331 |
#define UART0_CONTROL UCSR0B
|
|
|
332 |
#define UART0_DATA UDR0
|
|
|
333 |
#define UART0_UDRIE UDRIE0
|
|
|
334 |
#elif defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega640__)
|
|
|
335 |
/* ATmega with four USART */
|
|
|
336 |
#define ATMEGA_USART0
|
|
|
337 |
#define ATMEGA_USART1
|
|
|
338 |
#define ATMEGA_USART2
|
|
|
339 |
#define ATMEGA_USART3
|
|
|
340 |
#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
|
|
|
341 |
#define UART1_RECEIVE_INTERRUPT USART1_RX_vect
|
|
|
342 |
#define UART2_RECEIVE_INTERRUPT USART2_RX_vect
|
|
|
343 |
#define UART3_RECEIVE_INTERRUPT USART3_RX_vect
|
|
|
344 |
#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
|
|
|
345 |
#define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect
|
|
|
346 |
#define UART2_TRANSMIT_INTERRUPT USART2_UDRE_vect
|
|
|
347 |
#define UART3_TRANSMIT_INTERRUPT USART3_UDRE_vect
|
|
|
348 |
#define UART0_STATUS UCSR0A
|
|
|
349 |
#define UART0_CONTROL UCSR0B
|
|
|
350 |
#define UART0_DATA UDR0
|
|
|
351 |
#define UART0_UDRIE UDRIE0
|
|
|
352 |
#define UART1_STATUS UCSR1A
|
|
|
353 |
#define UART1_CONTROL UCSR1B
|
|
|
354 |
#define UART1_DATA UDR1
|
|
|
355 |
#define UART1_UDRIE UDRIE1
|
|
|
356 |
#define UART2_STATUS UCSR2A
|
|
|
357 |
#define UART2_CONTROL UCSR2B
|
|
|
358 |
#define UART2_DATA UDR2
|
|
|
359 |
#define UART2_UDRIE UDRIE2
|
|
|
360 |
#define UART3_STATUS UCSR3A
|
|
|
361 |
#define UART3_CONTROL UCSR3B
|
|
|
362 |
#define UART3_DATA UDR3
|
|
|
363 |
#define UART3_UDRIE UDRIE3
|
|
|
364 |
#elif defined(__AVR_ATmega644__)
|
|
|
365 |
/* ATmega with one USART */
|
|
|
366 |
#define ATMEGA_USART0
|
|
|
367 |
#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
|
|
|
368 |
#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
|
|
|
369 |
#define UART0_STATUS UCSR0A
|
|
|
370 |
#define UART0_CONTROL UCSR0B
|
|
|
371 |
#define UART0_DATA UDR0
|
|
|
372 |
#define UART0_UDRIE UDRIE0
|
|
|
373 |
#elif defined(__AVR_ATmega164P__) || defined(__AVR_ATmega324P__) || defined(__AVR_ATmega644P__) || \
|
|
|
374 |
defined(__AVR_ATmega1284P__)
|
|
|
375 |
/* ATmega with two USART */
|
|
|
376 |
#define ATMEGA_USART0
|
|
|
377 |
#define ATMEGA_USART1
|
|
|
378 |
#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
|
|
|
379 |
#define UART1_RECEIVE_INTERRUPT USART1_RX_vect
|
|
|
380 |
#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
|
|
|
381 |
#define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect
|
|
|
382 |
#define UART0_STATUS UCSR0A
|
|
|
383 |
#define UART0_CONTROL UCSR0B
|
|
|
384 |
#define UART0_DATA UDR0
|
|
|
385 |
#define UART0_UDRIE UDRIE0
|
|
|
386 |
#define UART1_STATUS UCSR1A
|
|
|
387 |
#define UART1_CONTROL UCSR1B
|
|
|
388 |
#define UART1_DATA UDR1
|
|
|
389 |
#define UART1_UDRIE UDRIE1
|
|
|
390 |
#else
|
|
|
391 |
#error "no UART definition for MCU available"
|
|
|
392 |
#endif
|
|
|
393 |
|
|
|
394 |
/*
|
|
|
395 |
* Module global variables
|
|
|
396 |
*/
|
|
|
397 |
|
|
|
398 |
#if defined( USART0_ENABLED )
|
|
|
399 |
#if defined( ATMEGA_USART ) || defined( ATMEGA_USART0 )
|
|
|
400 |
static volatile uint8_t UART_TxBuf[UART_TX0_BUFFER_SIZE];
|
|
|
401 |
static volatile uint8_t UART_RxBuf[UART_RX0_BUFFER_SIZE];
|
|
|
402 |
|
|
|
403 |
#if defined( USART0_LARGE_BUFFER )
|
|
|
404 |
static volatile uint16_t UART_TxHead;
|
|
|
405 |
static volatile uint16_t UART_TxTail;
|
|
|
406 |
static volatile uint16_t UART_RxHead;
|
|
|
407 |
static volatile uint16_t UART_RxTail;
|
|
|
408 |
static volatile uint8_t UART_LastRxError;
|
|
|
409 |
#else
|
|
|
410 |
static volatile uint8_t UART_TxHead;
|
|
|
411 |
static volatile uint8_t UART_TxTail;
|
|
|
412 |
static volatile uint8_t UART_RxHead;
|
|
|
413 |
static volatile uint8_t UART_RxTail;
|
|
|
414 |
static volatile uint8_t UART_LastRxError;
|
|
|
415 |
#endif
|
|
|
416 |
|
|
|
417 |
#endif
|
|
|
418 |
#endif
|
|
|
419 |
|
|
|
420 |
#if defined( USART1_ENABLED )
|
|
|
421 |
#if defined( ATMEGA_USART1 )
|
|
|
422 |
static volatile uint8_t UART1_TxBuf[UART_TX1_BUFFER_SIZE];
|
|
|
423 |
static volatile uint8_t UART1_RxBuf[UART_RX1_BUFFER_SIZE];
|
|
|
424 |
|
|
|
425 |
#if defined( USART1_LARGE_BUFFER )
|
|
|
426 |
static volatile uint16_t UART1_TxHead;
|
|
|
427 |
static volatile uint16_t UART1_TxTail;
|
|
|
428 |
static volatile uint16_t UART1_RxHead;
|
|
|
429 |
static volatile uint16_t UART1_RxTail;
|
|
|
430 |
static volatile uint8_t UART1_LastRxError;
|
|
|
431 |
#else
|
|
|
432 |
static volatile uint8_t UART1_TxHead;
|
|
|
433 |
static volatile uint8_t UART1_TxTail;
|
|
|
434 |
static volatile uint8_t UART1_RxHead;
|
|
|
435 |
static volatile uint8_t UART1_RxTail;
|
|
|
436 |
static volatile uint8_t UART1_LastRxError;
|
|
|
437 |
#endif
|
|
|
438 |
#endif
|
|
|
439 |
#endif
|
|
|
440 |
|
|
|
441 |
#if defined( USART2_ENABLED )
|
|
|
442 |
#if defined( ATMEGA_USART2 )
|
|
|
443 |
static volatile uint8_t UART2_TxBuf[UART_TX2_BUFFER_SIZE];
|
|
|
444 |
static volatile uint8_t UART2_RxBuf[UART_RX2_BUFFER_SIZE];
|
|
|
445 |
|
|
|
446 |
#if defined( USART2_LARGE_BUFFER )
|
|
|
447 |
static volatile uint16_t UART2_TxHead;
|
|
|
448 |
static volatile uint16_t UART2_TxTail;
|
|
|
449 |
static volatile uint16_t UART2_RxHead;
|
|
|
450 |
static volatile uint16_t UART2_RxTail;
|
|
|
451 |
static volatile uint8_t UART2_LastRxError;
|
|
|
452 |
#else
|
|
|
453 |
static volatile uint8_t UART2_TxHead;
|
|
|
454 |
static volatile uint8_t UART2_TxTail;
|
|
|
455 |
static volatile uint8_t UART2_RxHead;
|
|
|
456 |
static volatile uint8_t UART2_RxTail;
|
|
|
457 |
static volatile uint8_t UART2_LastRxError;
|
|
|
458 |
#endif
|
|
|
459 |
#endif
|
|
|
460 |
#endif
|
|
|
461 |
|
|
|
462 |
#if defined( USART3_ENABLED )
|
|
|
463 |
#if defined( ATMEGA_USART3 )
|
|
|
464 |
static volatile uint8_t UART3_TxBuf[UART_TX3_BUFFER_SIZE];
|
|
|
465 |
static volatile uint8_t UART3_RxBuf[UART_RX3_BUFFER_SIZE];
|
|
|
466 |
|
|
|
467 |
#if defined( USART3_LARGE_BUFFER )
|
|
|
468 |
static volatile uint16_t UART3_TxHead;
|
|
|
469 |
static volatile uint16_t UART3_TxTail;
|
|
|
470 |
static volatile uint16_t UART3_RxHead;
|
|
|
471 |
static volatile uint16_t UART3_RxTail;
|
|
|
472 |
static volatile uint8_t UART3_LastRxError;
|
|
|
473 |
#else
|
|
|
474 |
static volatile uint8_t UART3_TxHead;
|
|
|
475 |
static volatile uint8_t UART3_TxTail;
|
|
|
476 |
static volatile uint8_t UART3_RxHead;
|
|
|
477 |
static volatile uint8_t UART3_RxTail;
|
|
|
478 |
static volatile uint8_t UART3_LastRxError;
|
|
|
479 |
#endif
|
|
|
480 |
|
|
|
481 |
#endif
|
|
|
482 |
#endif
|
|
|
483 |
|
|
|
484 |
#if defined(AT90_UART) || defined(ATMEGA_USART) || defined(ATMEGA_USART0)
|
|
|
485 |
|
|
|
486 |
ISR(UART0_RECEIVE_INTERRUPT)
|
|
|
487 |
/*************************************************************************
|
|
|
488 |
Function: UART Receive Complete interrupt
|
|
|
489 |
Purpose: called when the UART has received a character
|
|
|
490 |
**************************************************************************/
|
|
|
491 |
{
|
|
|
492 |
uint16_t tmphead;
|
|
|
493 |
uint8_t data;
|
|
|
494 |
uint8_t usr;
|
|
|
495 |
uint8_t lastRxError;
|
|
|
496 |
|
|
|
497 |
/* read UART status register and UART data register */
|
|
|
498 |
usr = UART0_STATUS;
|
|
|
499 |
data = UART0_DATA;
|
|
|
500 |
|
|
|
501 |
/* */
|
|
|
502 |
#if defined( AT90_UART )
|
|
|
503 |
lastRxError = (usr & (_BV(FE)|_BV(DOR)) );
|
|
|
504 |
#elif defined( ATMEGA_USART )
|
|
|
505 |
lastRxError = (usr & (_BV(FE)|_BV(DOR)) );
|
|
|
506 |
#elif defined( ATMEGA_USART0 )
|
|
|
507 |
lastRxError = (usr & (_BV(FE0)|_BV(DOR0)) );
|
|
|
508 |
#elif defined ( ATMEGA_UART )
|
|
|
509 |
lastRxError = (usr & (_BV(FE)|_BV(DOR)) );
|
|
|
510 |
#endif
|
|
|
511 |
|
|
|
512 |
/* calculate buffer index */
|
|
|
513 |
tmphead = ( UART_RxHead + 1) & UART_RX0_BUFFER_MASK;
|
|
|
514 |
|
|
|
515 |
if ( tmphead == UART_RxTail ) {
|
|
|
516 |
/* error: receive buffer overflow */
|
|
|
517 |
lastRxError = UART_BUFFER_OVERFLOW >> 8;
|
|
|
518 |
} else {
|
|
|
519 |
/* store new index */
|
|
|
520 |
UART_RxHead = tmphead;
|
|
|
521 |
/* store received data in buffer */
|
|
|
522 |
UART_RxBuf[tmphead] = data;
|
|
|
523 |
}
|
|
|
524 |
UART_LastRxError = lastRxError;
|
|
|
525 |
}
|
|
|
526 |
|
|
|
527 |
|
|
|
528 |
ISR(UART0_TRANSMIT_INTERRUPT)
|
|
|
529 |
/*************************************************************************
|
|
|
530 |
Function: UART Data Register Empty interrupt
|
|
|
531 |
Purpose: called when the UART is ready to transmit the next byte
|
|
|
532 |
**************************************************************************/
|
|
|
533 |
{
|
|
|
534 |
uint16_t tmptail;
|
|
|
535 |
|
|
|
536 |
if ( UART_TxHead != UART_TxTail) {
|
|
|
537 |
/* calculate and store new buffer index */
|
|
|
538 |
tmptail = (UART_TxTail + 1) & UART_TX0_BUFFER_MASK;
|
|
|
539 |
UART_TxTail = tmptail;
|
|
|
540 |
/* get one byte from buffer and write it to UART */
|
|
|
541 |
UART0_DATA = UART_TxBuf[tmptail]; /* start transmission */
|
|
|
542 |
} else {
|
|
|
543 |
/* tx buffer empty, disable UDRE interrupt */
|
|
|
544 |
UART0_CONTROL &= ~_BV(UART0_UDRIE);
|
|
|
545 |
}
|
|
|
546 |
}
|
|
|
547 |
|
|
|
548 |
|
|
|
549 |
/*************************************************************************
|
|
|
550 |
Function: uart0_init()
|
|
|
551 |
Purpose: initialize UART and set baudrate
|
|
|
552 |
Input: baudrate using macro UART_BAUD_SELECT()
|
|
|
553 |
Returns: none
|
|
|
554 |
**************************************************************************/
|
|
|
555 |
void uart0_init(uint16_t baudrate)
|
|
|
556 |
{
|
|
|
557 |
UART_TxHead = 0;
|
|
|
558 |
UART_TxTail = 0;
|
|
|
559 |
UART_RxHead = 0;
|
|
|
560 |
UART_RxTail = 0;
|
|
|
561 |
|
|
|
562 |
#if defined( AT90_UART )
|
|
|
563 |
/* set baud rate */
|
|
|
564 |
UBRR = (uint8_t)baudrate;
|
|
|
565 |
|
|
|
566 |
/* enable UART receiver and transmitter and receive complete interrupt */
|
|
|
567 |
UART0_CONTROL = _BV(RXCIE)|_BV(RXEN)|_BV(TXEN);
|
|
|
568 |
|
|
|
569 |
#elif defined (ATMEGA_USART)
|
|
|
570 |
/* Set baud rate */
|
|
|
571 |
if ( baudrate & 0x8000 ) {
|
|
|
572 |
UART0_STATUS = (1<<U2X); //Enable 2x speed
|
|
|
573 |
baudrate &= ~0x8000;
|
|
|
574 |
}
|
|
|
575 |
UBRRH = (uint8_t)(baudrate>>8);
|
|
|
576 |
UBRRL = (uint8_t) baudrate;
|
|
|
577 |
|
|
|
578 |
/* Enable USART receiver and transmitter and receive complete interrupt */
|
|
|
579 |
UART0_CONTROL = _BV(RXCIE)|(1<<RXEN)|(1<<TXEN);
|
|
|
580 |
|
|
|
581 |
/* Set frame format: asynchronous, 8data, no parity, 1stop bit */
|
|
|
582 |
#ifdef URSEL
|
|
|
583 |
UCSRC = (1<<URSEL)|(3<<UCSZ0);
|
|
|
584 |
#else
|
|
|
585 |
UCSRC = (3<<UCSZ0);
|
|
|
586 |
#endif
|
|
|
587 |
|
|
|
588 |
#elif defined ( ATMEGA_USART0 )
|
|
|
589 |
/* Set baud rate */
|
|
|
590 |
if ( baudrate & 0x8000 ) {
|
|
|
591 |
UART0_STATUS = (1<<U2X0); //Enable 2x speed
|
|
|
592 |
baudrate &= ~0x8000;
|
|
|
593 |
}
|
|
|
594 |
UBRR0H = (uint8_t)(baudrate>>8);
|
|
|
595 |
UBRR0L = (uint8_t) baudrate;
|
|
|
596 |
|
|
|
597 |
/* Enable USART receiver and transmitter and receive complete interrupt */
|
|
|
598 |
UART0_CONTROL = _BV(RXCIE0)|(1<<RXEN0)|(1<<TXEN0);
|
|
|
599 |
|
|
|
600 |
/* Set frame format: asynchronous, 8data, no parity, 1stop bit */
|
|
|
601 |
#ifdef URSEL0
|
|
|
602 |
UCSR0C = (1<<URSEL0)|(3<<UCSZ00);
|
|
|
603 |
#else
|
|
|
604 |
UCSR0C = (3<<UCSZ00);
|
|
|
605 |
#endif
|
|
|
606 |
|
|
|
607 |
#elif defined ( ATMEGA_UART )
|
|
|
608 |
/* set baud rate */
|
|
|
609 |
if ( baudrate & 0x8000 ) {
|
|
|
610 |
UART0_STATUS = (1<<U2X); //Enable 2x speed
|
|
|
611 |
baudrate &= ~0x8000;
|
|
|
612 |
}
|
|
|
613 |
UBRRHI = (uint8_t)(baudrate>>8);
|
|
|
614 |
UBRR = (uint8_t) baudrate;
|
|
|
615 |
|
|
|
616 |
/* Enable UART receiver and transmitter and receive complete interrupt */
|
|
|
617 |
UART0_CONTROL = _BV(RXCIE)|(1<<RXEN)|(1<<TXEN);
|
|
|
618 |
|
|
|
619 |
#endif
|
|
|
620 |
|
|
|
621 |
} /* uart0_init */
|
|
|
622 |
|
|
|
623 |
|
|
|
624 |
/*************************************************************************
|
|
|
625 |
Function: uart0_getc()
|
|
|
626 |
Purpose: return byte from ringbuffer
|
|
|
627 |
Returns: lower byte: received byte from ringbuffer
|
|
|
628 |
higher byte: last receive error
|
|
|
629 |
**************************************************************************/
|
|
|
630 |
uint16_t uart0_getc(void)
|
|
|
631 |
{
|
|
|
632 |
uint16_t tmptail;
|
|
|
633 |
uint8_t data;
|
|
|
634 |
|
|
|
635 |
if ( UART_RxHead == UART_RxTail ) {
|
|
|
636 |
return UART_NO_DATA; /* no data available */
|
|
|
637 |
}
|
|
|
638 |
|
|
|
639 |
/* calculate /store buffer index */
|
|
|
640 |
tmptail = (UART_RxTail + 1) & UART_RX0_BUFFER_MASK;
|
|
|
641 |
UART_RxTail = tmptail;
|
|
|
642 |
|
|
|
643 |
/* get data from receive buffer */
|
|
|
644 |
data = UART_RxBuf[tmptail];
|
|
|
645 |
|
|
|
646 |
return (UART_LastRxError << 8) + data;
|
|
|
647 |
|
|
|
648 |
} /* uart0_getc */
|
|
|
649 |
|
|
|
650 |
/*************************************************************************
|
|
|
651 |
Function: uart0_peek()
|
|
|
652 |
Purpose: Returns the next byte (character) of incoming UART data without
|
|
|
653 |
removing it from the ring buffer. That is, successive calls to
|
|
|
654 |
uartN_peek() will return the same character, as will the next
|
|
|
655 |
call to uartN_getc()
|
|
|
656 |
Returns: lower byte: next byte in ring buffer
|
|
|
657 |
higher byte: last receive error
|
|
|
658 |
**************************************************************************/
|
|
|
659 |
uint16_t uart0_peek(void)
|
|
|
660 |
{
|
|
|
661 |
uint16_t tmptail;
|
|
|
662 |
uint8_t data;
|
|
|
663 |
|
|
|
664 |
if ( UART_RxHead == UART_RxTail ) {
|
|
|
665 |
return UART_NO_DATA; /* no data available */
|
|
|
666 |
}
|
|
|
667 |
|
|
|
668 |
tmptail = (UART_RxTail + 1) & UART_RX0_BUFFER_MASK;
|
|
|
669 |
|
|
|
670 |
/* get data from receive buffer */
|
|
|
671 |
data = UART_RxBuf[tmptail];
|
|
|
672 |
|
|
|
673 |
return (UART_LastRxError << 8) + data;
|
|
|
674 |
|
|
|
675 |
} /* uart0_peek */
|
|
|
676 |
|
|
|
677 |
/*************************************************************************
|
|
|
678 |
Function: uart0_putc()
|
|
|
679 |
Purpose: write byte to ringbuffer for transmitting via UART
|
|
|
680 |
Input: byte to be transmitted
|
|
|
681 |
Returns: none
|
|
|
682 |
**************************************************************************/
|
|
|
683 |
void uart0_putc(uint8_t data)
|
|
|
684 |
{
|
|
|
685 |
uint16_t tmphead;
|
|
|
686 |
|
|
|
687 |
tmphead = (UART_TxHead + 1) & UART_TX0_BUFFER_MASK;
|
|
|
688 |
|
|
|
689 |
while ( tmphead == UART_TxTail ) {
|
|
|
690 |
;/* wait for free space in buffer */
|
|
|
691 |
}
|
|
|
692 |
|
|
|
693 |
UART_TxBuf[tmphead] = data;
|
|
|
694 |
UART_TxHead = tmphead;
|
|
|
695 |
|
|
|
696 |
/* enable UDRE interrupt */
|
|
|
697 |
UART0_CONTROL |= _BV(UART0_UDRIE);
|
|
|
698 |
|
|
|
699 |
} /* uart0_putc */
|
|
|
700 |
|
|
|
701 |
|
|
|
702 |
/*************************************************************************
|
|
|
703 |
Function: uart0_puts()
|
|
|
704 |
Purpose: transmit string to UART
|
|
|
705 |
Input: string to be transmitted
|
|
|
706 |
Returns: none
|
|
|
707 |
**************************************************************************/
|
|
|
708 |
void uart0_puts(const char *s )
|
|
|
709 |
{
|
|
|
710 |
while (*s) {
|
|
|
711 |
uart0_putc(*s++);
|
|
|
712 |
}
|
|
|
713 |
|
|
|
714 |
} /* uart0_puts */
|
|
|
715 |
|
|
|
716 |
|
|
|
717 |
/*************************************************************************
|
|
|
718 |
Function: uart0_puts_p()
|
|
|
719 |
Purpose: transmit string from program memory to UART
|
|
|
720 |
Input: program memory string to be transmitted
|
|
|
721 |
Returns: none
|
|
|
722 |
**************************************************************************/
|
|
|
723 |
void uart0_puts_p(const char *progmem_s )
|
|
|
724 |
{
|
|
|
725 |
register char c;
|
|
|
726 |
|
|
|
727 |
while ( (c = pgm_read_byte(progmem_s++)) ) {
|
|
|
728 |
uart0_putc(c);
|
|
|
729 |
}
|
|
|
730 |
|
|
|
731 |
} /* uart0_puts_p */
|
|
|
732 |
|
|
|
733 |
|
|
|
734 |
|
|
|
735 |
/*************************************************************************
|
|
|
736 |
Function: uart0_available()
|
|
|
737 |
Purpose: Determine the number of bytes waiting in the receive buffer
|
|
|
738 |
Input: None
|
|
|
739 |
Returns: Integer number of bytes in the receive buffer
|
|
|
740 |
**************************************************************************/
|
|
|
741 |
int uart0_available(void)
|
|
|
742 |
{
|
|
|
743 |
return (UART_RX0_BUFFER_MASK + UART_RxHead - UART_RxTail) % UART_RX0_BUFFER_MASK;
|
|
|
744 |
} /* uart0_available */
|
|
|
745 |
|
|
|
746 |
/*************************************************************************
|
|
|
747 |
Function: uart0_flush()
|
|
|
748 |
Purpose: Flush bytes waiting the receive buffer. Acutally ignores them.
|
|
|
749 |
Input: None
|
|
|
750 |
Returns: None
|
|
|
751 |
**************************************************************************/
|
|
|
752 |
void uart0_flush(void)
|
|
|
753 |
{
|
|
|
754 |
UART_RxHead = UART_RxTail;
|
|
|
755 |
} /* uart0_flush */
|
|
|
756 |
|
|
|
757 |
#endif
|
|
|
758 |
|
|
|
759 |
#if defined( USART1_ENABLED )
|
|
|
760 |
|
|
|
761 |
/*
|
|
|
762 |
* these functions are only for ATmegas with two USART
|
|
|
763 |
*/
|
|
|
764 |
#if defined( ATMEGA_USART1 )
|
|
|
765 |
|
|
|
766 |
ISR(UART1_RECEIVE_INTERRUPT)
|
|
|
767 |
/*************************************************************************
|
|
|
768 |
Function: UART1 Receive Complete interrupt
|
|
|
769 |
Purpose: called when the UART1 has received a character
|
|
|
770 |
**************************************************************************/
|
|
|
771 |
{
|
|
|
772 |
uint16_t tmphead;
|
|
|
773 |
uint8_t data;
|
|
|
774 |
uint8_t usr;
|
|
|
775 |
uint8_t lastRxError;
|
|
|
776 |
|
|
|
777 |
/* read UART status register and UART data register */
|
|
|
778 |
usr = UART1_STATUS;
|
|
|
779 |
data = UART1_DATA;
|
|
|
780 |
|
|
|
781 |
/* */
|
|
|
782 |
lastRxError = (usr & (_BV(FE1)|_BV(DOR1)) );
|
|
|
783 |
|
|
|
784 |
/* calculate buffer index */
|
|
|
785 |
tmphead = ( UART1_RxHead + 1) & UART_RX1_BUFFER_MASK;
|
|
|
786 |
|
|
|
787 |
if ( tmphead == UART1_RxTail ) {
|
|
|
788 |
/* error: receive buffer overflow */
|
|
|
789 |
lastRxError = UART_BUFFER_OVERFLOW >> 8;
|
|
|
790 |
} else {
|
|
|
791 |
/* store new index */
|
|
|
792 |
UART1_RxHead = tmphead;
|
|
|
793 |
/* store received data in buffer */
|
|
|
794 |
UART1_RxBuf[tmphead] = data;
|
|
|
795 |
}
|
|
|
796 |
UART1_LastRxError = lastRxError;
|
|
|
797 |
}
|
|
|
798 |
|
|
|
799 |
|
|
|
800 |
ISR(UART1_TRANSMIT_INTERRUPT)
|
|
|
801 |
/*************************************************************************
|
|
|
802 |
Function: UART1 Data Register Empty interrupt
|
|
|
803 |
Purpose: called when the UART1 is ready to transmit the next byte
|
|
|
804 |
**************************************************************************/
|
|
|
805 |
{
|
|
|
806 |
uint16_t tmptail;
|
|
|
807 |
|
|
|
808 |
if ( UART1_TxHead != UART1_TxTail) {
|
|
|
809 |
/* calculate and store new buffer index */
|
|
|
810 |
tmptail = (UART1_TxTail + 1) & UART_TX1_BUFFER_MASK;
|
|
|
811 |
UART1_TxTail = tmptail;
|
|
|
812 |
/* get one byte from buffer and write it to UART */
|
|
|
813 |
UART1_DATA = UART1_TxBuf[tmptail]; /* start transmission */
|
|
|
814 |
} else {
|
|
|
815 |
/* tx buffer empty, disable UDRE interrupt */
|
|
|
816 |
UART1_CONTROL &= ~_BV(UART1_UDRIE);
|
|
|
817 |
}
|
|
|
818 |
}
|
|
|
819 |
|
|
|
820 |
|
|
|
821 |
/*************************************************************************
|
|
|
822 |
Function: uart1_init()
|
|
|
823 |
Purpose: initialize UART1 and set baudrate
|
|
|
824 |
Input: baudrate using macro UART_BAUD_SELECT()
|
|
|
825 |
Returns: none
|
|
|
826 |
**************************************************************************/
|
|
|
827 |
void uart1_init(uint16_t baudrate)
|
|
|
828 |
{
|
|
|
829 |
UART1_TxHead = 0;
|
|
|
830 |
UART1_TxTail = 0;
|
|
|
831 |
UART1_RxHead = 0;
|
|
|
832 |
UART1_RxTail = 0;
|
|
|
833 |
|
|
|
834 |
/* Set baud rate */
|
|
|
835 |
if ( baudrate & 0x8000 ) {
|
|
|
836 |
UART1_STATUS = (1<<U2X1); //Enable 2x speed
|
|
|
837 |
baudrate &= ~0x8000;
|
|
|
838 |
}
|
|
|
839 |
UBRR1H = (uint8_t)(baudrate>>8);
|
|
|
840 |
UBRR1L = (uint8_t) baudrate;
|
|
|
841 |
|
|
|
842 |
/* Enable USART receiver and transmitter and receive complete interrupt */
|
|
|
843 |
UART1_CONTROL = _BV(RXCIE1)|(1<<RXEN1)|(1<<TXEN1);
|
|
|
844 |
|
|
|
845 |
/* Set frame format: asynchronous, 8data, no parity, 1stop bit */
|
|
|
846 |
#ifdef URSEL1
|
|
|
847 |
UCSR1C = (1<<URSEL1)|(3<<UCSZ10);
|
|
|
848 |
#else
|
|
|
849 |
UCSR1C = (3<<UCSZ10);
|
|
|
850 |
#endif
|
|
|
851 |
} /* uart_init */
|
|
|
852 |
|
|
|
853 |
|
|
|
854 |
/*************************************************************************
|
|
|
855 |
Function: uart1_getc()
|
|
|
856 |
Purpose: return byte from ringbuffer
|
|
|
857 |
Returns: lower byte: received byte from ringbuffer
|
|
|
858 |
higher byte: last receive error
|
|
|
859 |
**************************************************************************/
|
|
|
860 |
uint16_t uart1_getc(void)
|
|
|
861 |
{
|
|
|
862 |
uint16_t tmptail;
|
|
|
863 |
uint8_t data;
|
|
|
864 |
|
|
|
865 |
if ( UART1_RxHead == UART1_RxTail ) {
|
|
|
866 |
return UART_NO_DATA; /* no data available */
|
|
|
867 |
}
|
|
|
868 |
|
|
|
869 |
/* calculate /store buffer index */
|
|
|
870 |
tmptail = (UART1_RxTail + 1) & UART_RX1_BUFFER_MASK;
|
|
|
871 |
UART1_RxTail = tmptail;
|
|
|
872 |
|
|
|
873 |
/* get data from receive buffer */
|
|
|
874 |
data = UART1_RxBuf[tmptail];
|
|
|
875 |
|
|
|
876 |
return (UART1_LastRxError << 8) + data;
|
|
|
877 |
|
|
|
878 |
} /* uart1_getc */
|
|
|
879 |
|
|
|
880 |
/*************************************************************************
|
|
|
881 |
Function: uart1_peek()
|
|
|
882 |
Purpose: Returns the next byte (character) of incoming UART data without
|
|
|
883 |
removing it from the ring buffer. That is, successive calls to
|
|
|
884 |
uartN_peek() will return the same character, as will the next
|
|
|
885 |
call to uartN_getc()
|
|
|
886 |
Returns: lower byte: next byte in ring buffer
|
|
|
887 |
higher byte: last receive error
|
|
|
888 |
**************************************************************************/
|
|
|
889 |
uint16_t uart1_peek(void)
|
|
|
890 |
{
|
|
|
891 |
uint16_t tmptail;
|
|
|
892 |
uint8_t data;
|
|
|
893 |
|
|
|
894 |
if ( UART1_RxHead == UART1_RxTail ) {
|
|
|
895 |
return UART_NO_DATA; /* no data available */
|
|
|
896 |
}
|
|
|
897 |
|
|
|
898 |
tmptail = (UART1_RxTail + 1) & UART_RX1_BUFFER_MASK;
|
|
|
899 |
|
|
|
900 |
/* get data from receive buffer */
|
|
|
901 |
data = UART1_RxBuf[tmptail];
|
|
|
902 |
|
|
|
903 |
return (UART1_LastRxError << 8) + data;
|
|
|
904 |
|
|
|
905 |
} /* uart1_peek */
|
|
|
906 |
|
|
|
907 |
/*************************************************************************
|
|
|
908 |
Function: uart1_putc()
|
|
|
909 |
Purpose: write byte to ringbuffer for transmitting via UART
|
|
|
910 |
Input: byte to be transmitted
|
|
|
911 |
Returns: none
|
|
|
912 |
**************************************************************************/
|
|
|
913 |
void uart1_putc(uint8_t data)
|
|
|
914 |
{
|
|
|
915 |
uint16_t tmphead;
|
|
|
916 |
|
|
|
917 |
tmphead = (UART1_TxHead + 1) & UART_TX1_BUFFER_MASK;
|
|
|
918 |
|
|
|
919 |
while ( tmphead == UART1_TxTail ) {
|
|
|
920 |
;/* wait for free space in buffer */
|
|
|
921 |
}
|
|
|
922 |
|
|
|
923 |
UART1_TxBuf[tmphead] = data;
|
|
|
924 |
UART1_TxHead = tmphead;
|
|
|
925 |
|
|
|
926 |
/* enable UDRE interrupt */
|
|
|
927 |
UART1_CONTROL |= _BV(UART1_UDRIE);
|
|
|
928 |
|
|
|
929 |
} /* uart1_putc */
|
|
|
930 |
|
|
|
931 |
|
|
|
932 |
/*************************************************************************
|
|
|
933 |
Function: uart1_puts()
|
|
|
934 |
Purpose: transmit string to UART1
|
|
|
935 |
Input: string to be transmitted
|
|
|
936 |
Returns: none
|
|
|
937 |
**************************************************************************/
|
|
|
938 |
void uart1_puts(const char *s )
|
|
|
939 |
{
|
|
|
940 |
while (*s) {
|
|
|
941 |
uart1_putc(*s++);
|
|
|
942 |
}
|
|
|
943 |
|
|
|
944 |
} /* uart1_puts */
|
|
|
945 |
|
|
|
946 |
|
|
|
947 |
/*************************************************************************
|
|
|
948 |
Function: uart1_puts_p()
|
|
|
949 |
Purpose: transmit string from program memory to UART1
|
|
|
950 |
Input: program memory string to be transmitted
|
|
|
951 |
Returns: none
|
|
|
952 |
**************************************************************************/
|
|
|
953 |
void uart1_puts_p(const char *progmem_s )
|
|
|
954 |
{
|
|
|
955 |
register char c;
|
|
|
956 |
|
|
|
957 |
while ( (c = pgm_read_byte(progmem_s++)) ) {
|
|
|
958 |
uart1_putc(c);
|
|
|
959 |
}
|
|
|
960 |
|
|
|
961 |
} /* uart1_puts_p */
|
|
|
962 |
|
|
|
963 |
|
|
|
964 |
|
|
|
965 |
/*************************************************************************
|
|
|
966 |
Function: uart1_available()
|
|
|
967 |
Purpose: Determine the number of bytes waiting in the receive buffer
|
|
|
968 |
Input: None
|
|
|
969 |
Returns: Integer number of bytes in the receive buffer
|
|
|
970 |
**************************************************************************/
|
|
|
971 |
int uart1_available(void)
|
|
|
972 |
{
|
|
|
973 |
return (UART_RX1_BUFFER_MASK + UART1_RxHead - UART1_RxTail) % UART_RX1_BUFFER_MASK;
|
|
|
974 |
} /* uart1_available */
|
|
|
975 |
|
|
|
976 |
|
|
|
977 |
|
|
|
978 |
/*************************************************************************
|
|
|
979 |
Function: uart1_flush()
|
|
|
980 |
Purpose: Flush bytes waiting the receive buffer. Acutally ignores them.
|
|
|
981 |
Input: None
|
|
|
982 |
Returns: None
|
|
|
983 |
**************************************************************************/
|
|
|
984 |
void uart1_flush(void)
|
|
|
985 |
{
|
|
|
986 |
UART1_RxHead = UART1_RxTail;
|
|
|
987 |
} /* uart1_flush */
|
|
|
988 |
|
|
|
989 |
#endif
|
|
|
990 |
|
|
|
991 |
#endif /* defined( USART1_ENABLED ) */
|
|
|
992 |
|
|
|
993 |
#if defined( USART2_ENABLED )
|
|
|
994 |
|
|
|
995 |
/*
|
|
|
996 |
* these functions are only for ATmegas with four USART
|
|
|
997 |
*/
|
|
|
998 |
#if defined( ATMEGA_USART2 )
|
|
|
999 |
|
|
|
1000 |
ISR(UART2_RECEIVE_INTERRUPT)
|
|
|
1001 |
/*************************************************************************
|
|
|
1002 |
Function: UART2 Receive Complete interrupt
|
|
|
1003 |
Purpose: called when the UART2 has received a character
|
|
|
1004 |
**************************************************************************/
|
|
|
1005 |
{
|
|
|
1006 |
uint16_t tmphead;
|
|
|
1007 |
uint8_t data;
|
|
|
1008 |
uint8_t usr;
|
|
|
1009 |
uint8_t lastRxError;
|
|
|
1010 |
|
|
|
1011 |
|
|
|
1012 |
/* read UART status register and UART data register */
|
|
|
1013 |
usr = UART2_STATUS;
|
|
|
1014 |
data = UART2_DATA;
|
|
|
1015 |
|
|
|
1016 |
/* */
|
|
|
1017 |
lastRxError = (usr & (_BV(FE2)|_BV(DOR2)) );
|
|
|
1018 |
|
|
|
1019 |
/* calculate buffer index */
|
|
|
1020 |
tmphead = ( UART2_RxHead + 1) & UART_RX2_BUFFER_MASK;
|
|
|
1021 |
|
|
|
1022 |
if ( tmphead == UART2_RxTail ) {
|
|
|
1023 |
/* error: receive buffer overflow */
|
|
|
1024 |
lastRxError = UART_BUFFER_OVERFLOW >> 8;
|
|
|
1025 |
} else {
|
|
|
1026 |
/* store new index */
|
|
|
1027 |
UART2_RxHead = tmphead;
|
|
|
1028 |
/* store received data in buffer */
|
|
|
1029 |
UART2_RxBuf[tmphead] = data;
|
|
|
1030 |
}
|
|
|
1031 |
UART2_LastRxError = lastRxError;
|
|
|
1032 |
}
|
|
|
1033 |
|
|
|
1034 |
|
|
|
1035 |
ISR(UART2_TRANSMIT_INTERRUPT)
|
|
|
1036 |
/*************************************************************************
|
|
|
1037 |
Function: UART2 Data Register Empty interrupt
|
|
|
1038 |
Purpose: called when the UART2 is ready to transmit the next byte
|
|
|
1039 |
**************************************************************************/
|
|
|
1040 |
{
|
|
|
1041 |
uint16_t tmptail;
|
|
|
1042 |
|
|
|
1043 |
|
|
|
1044 |
if ( UART2_TxHead != UART2_TxTail) {
|
|
|
1045 |
/* calculate and store new buffer index */
|
|
|
1046 |
tmptail = (UART2_TxTail + 1) & UART_TX2_BUFFER_MASK;
|
|
|
1047 |
UART2_TxTail = tmptail;
|
|
|
1048 |
/* get one byte from buffer and write it to UART */
|
|
|
1049 |
UART2_DATA = UART2_TxBuf[tmptail]; /* start transmission */
|
|
|
1050 |
} else {
|
|
|
1051 |
/* tx buffer empty, disable UDRE interrupt */
|
|
|
1052 |
UART2_CONTROL &= ~_BV(UART2_UDRIE);
|
|
|
1053 |
}
|
|
|
1054 |
}
|
|
|
1055 |
|
|
|
1056 |
|
|
|
1057 |
/*************************************************************************
|
|
|
1058 |
Function: uart2_init()
|
|
|
1059 |
Purpose: initialize UART2 and set baudrate
|
|
|
1060 |
Input: baudrate using macro UART_BAUD_SELECT()
|
|
|
1061 |
Returns: none
|
|
|
1062 |
**************************************************************************/
|
|
|
1063 |
void uart2_init(uint16_t baudrate)
|
|
|
1064 |
{
|
|
|
1065 |
UART2_TxHead = 0;
|
|
|
1066 |
UART2_TxTail = 0;
|
|
|
1067 |
UART2_RxHead = 0;
|
|
|
1068 |
UART2_RxTail = 0;
|
|
|
1069 |
|
|
|
1070 |
|
|
|
1071 |
/* Set baud rate */
|
|
|
1072 |
if ( baudrate & 0x8000 ) {
|
|
|
1073 |
UART2_STATUS = (1<<U2X2); //Enable 2x speed
|
|
|
1074 |
baudrate &= ~0x8000;
|
|
|
1075 |
}
|
|
|
1076 |
UBRR2H = (uint8_t)(baudrate>>8);
|
|
|
1077 |
UBRR2L = (uint8_t) baudrate;
|
|
|
1078 |
|
|
|
1079 |
/* Enable USART receiver and transmitter and receive complete interrupt */
|
|
|
1080 |
UART2_CONTROL = _BV(RXCIE2)|(1<<RXEN2)|(1<<TXEN2);
|
|
|
1081 |
|
|
|
1082 |
/* Set frame format: asynchronous, 8data, no parity, 1stop bit */
|
|
|
1083 |
#ifdef URSEL2
|
|
|
1084 |
UCSR2C = (1<<URSEL2)|(3<<UCSZ20);
|
|
|
1085 |
#else
|
|
|
1086 |
UCSR2C = (3<<UCSZ20);
|
|
|
1087 |
#endif
|
|
|
1088 |
} /* uart_init */
|
|
|
1089 |
|
|
|
1090 |
|
|
|
1091 |
/*************************************************************************
|
|
|
1092 |
Function: uart2_getc()
|
|
|
1093 |
Purpose: return byte from ringbuffer
|
|
|
1094 |
Returns: lower byte: received byte from ringbuffer
|
|
|
1095 |
higher byte: last receive error
|
|
|
1096 |
**************************************************************************/
|
|
|
1097 |
uint16_t uart2_getc(void)
|
|
|
1098 |
{
|
|
|
1099 |
uint16_t tmptail;
|
|
|
1100 |
uint8_t data;
|
|
|
1101 |
|
|
|
1102 |
if ( UART2_RxHead == UART2_RxTail ) {
|
|
|
1103 |
return UART_NO_DATA; /* no data available */
|
|
|
1104 |
}
|
|
|
1105 |
|
|
|
1106 |
/* calculate /store buffer index */
|
|
|
1107 |
tmptail = (UART2_RxTail + 1) & UART_RX2_BUFFER_MASK;
|
|
|
1108 |
UART2_RxTail = tmptail;
|
|
|
1109 |
|
|
|
1110 |
/* get data from receive buffer */
|
|
|
1111 |
data = UART2_RxBuf[tmptail];
|
|
|
1112 |
|
|
|
1113 |
return (UART2_LastRxError << 8) + data;
|
|
|
1114 |
|
|
|
1115 |
} /* uart2_getc */
|
|
|
1116 |
|
|
|
1117 |
/*************************************************************************
|
|
|
1118 |
Function: uart2_peek()
|
|
|
1119 |
Purpose: Returns the next byte (character) of incoming UART data without
|
|
|
1120 |
removing it from the ring buffer. That is, successive calls to
|
|
|
1121 |
uartN_peek() will return the same character, as will the next
|
|
|
1122 |
call to uartN_getc()
|
|
|
1123 |
Returns: lower byte: next byte in ring buffer
|
|
|
1124 |
higher byte: last receive error
|
|
|
1125 |
**************************************************************************/
|
|
|
1126 |
uint16_t uart2_peek(void)
|
|
|
1127 |
{
|
|
|
1128 |
uint16_t tmptail;
|
|
|
1129 |
uint8_t data;
|
|
|
1130 |
|
|
|
1131 |
|
|
|
1132 |
if ( UART2_RxHead == UART2_RxTail ) {
|
|
|
1133 |
return UART_NO_DATA; /* no data available */
|
|
|
1134 |
}
|
|
|
1135 |
|
|
|
1136 |
tmptail = (UART2_RxTail + 1) & UART_RX2_BUFFER_MASK;
|
|
|
1137 |
|
|
|
1138 |
/* get data from receive buffer */
|
|
|
1139 |
data = UART2_RxBuf[tmptail];
|
|
|
1140 |
|
|
|
1141 |
return (UART2_LastRxError << 8) + data;
|
|
|
1142 |
|
|
|
1143 |
} /* uart2_peek */
|
|
|
1144 |
|
|
|
1145 |
/*************************************************************************
|
|
|
1146 |
Function: uart2_putc()
|
|
|
1147 |
Purpose: write byte to ringbuffer for transmitting via UART
|
|
|
1148 |
Input: byte to be transmitted
|
|
|
1149 |
Returns: none
|
|
|
1150 |
**************************************************************************/
|
|
|
1151 |
void uart2_putc(uint8_t data)
|
|
|
1152 |
{
|
|
|
1153 |
uint16_t tmphead;
|
|
|
1154 |
|
|
|
1155 |
|
|
|
1156 |
tmphead = (UART2_TxHead + 1) & UART_TX2_BUFFER_MASK;
|
|
|
1157 |
|
|
|
1158 |
while ( tmphead == UART2_TxTail ) {
|
|
|
1159 |
;/* wait for free space in buffer */
|
|
|
1160 |
}
|
|
|
1161 |
|
|
|
1162 |
UART2_TxBuf[tmphead] = data;
|
|
|
1163 |
UART2_TxHead = tmphead;
|
|
|
1164 |
|
|
|
1165 |
/* enable UDRE interrupt */
|
|
|
1166 |
UART2_CONTROL |= _BV(UART2_UDRIE);
|
|
|
1167 |
|
|
|
1168 |
} /* uart2_putc */
|
|
|
1169 |
|
|
|
1170 |
|
|
|
1171 |
/*************************************************************************
|
|
|
1172 |
Function: uart2_puts()
|
|
|
1173 |
Purpose: transmit string to UART2
|
|
|
1174 |
Input: string to be transmitted
|
|
|
1175 |
Returns: none
|
|
|
1176 |
**************************************************************************/
|
|
|
1177 |
void uart2_puts(const char *s )
|
|
|
1178 |
{
|
|
|
1179 |
while (*s)
|
|
|
1180 |
uart2_putc(*s++);
|
|
|
1181 |
|
|
|
1182 |
} /* uart2_puts */
|
|
|
1183 |
|
|
|
1184 |
|
|
|
1185 |
/*************************************************************************
|
|
|
1186 |
Function: uart2_puts_p()
|
|
|
1187 |
Purpose: transmit string from program memory to UART2
|
|
|
1188 |
Input: program memory string to be transmitted
|
|
|
1189 |
Returns: none
|
|
|
1190 |
**************************************************************************/
|
|
|
1191 |
void uart2_puts_p(const char *progmem_s )
|
|
|
1192 |
{
|
|
|
1193 |
register char c;
|
|
|
1194 |
|
|
|
1195 |
while ( (c = pgm_read_byte(progmem_s++)) ) {
|
|
|
1196 |
uart2_putc(c);
|
|
|
1197 |
}
|
|
|
1198 |
|
|
|
1199 |
} /* uart2_puts_p */
|
|
|
1200 |
|
|
|
1201 |
|
|
|
1202 |
|
|
|
1203 |
/*************************************************************************
|
|
|
1204 |
Function: uart2_available()
|
|
|
1205 |
Purpose: Determine the number of bytes waiting in the receive buffer
|
|
|
1206 |
Input: None
|
|
|
1207 |
Returns: Integer number of bytes in the receive buffer
|
|
|
1208 |
**************************************************************************/
|
|
|
1209 |
int uart2_available(void)
|
|
|
1210 |
{
|
|
|
1211 |
return (UART_RX2_BUFFER_MASK + UART2_RxHead - UART2_RxTail) % UART_RX2_BUFFER_MASK;
|
|
|
1212 |
} /* uart2_available */
|
|
|
1213 |
|
|
|
1214 |
|
|
|
1215 |
|
|
|
1216 |
/*************************************************************************
|
|
|
1217 |
Function: uart2_flush()
|
|
|
1218 |
Purpose: Flush bytes waiting the receive buffer. Acutally ignores them.
|
|
|
1219 |
Input: None
|
|
|
1220 |
Returns: None
|
|
|
1221 |
**************************************************************************/
|
|
|
1222 |
void uart2_flush(void)
|
|
|
1223 |
{
|
|
|
1224 |
UART2_RxHead = UART2_RxTail;
|
|
|
1225 |
} /* uart2_flush */
|
|
|
1226 |
|
|
|
1227 |
#endif
|
|
|
1228 |
|
|
|
1229 |
#endif /* defined( USART2_ENABLED ) */
|
|
|
1230 |
|
|
|
1231 |
#if defined( USART3_ENABLED )
|
|
|
1232 |
|
|
|
1233 |
/*
|
|
|
1234 |
* these functions are only for ATmegas with four USART
|
|
|
1235 |
*/
|
|
|
1236 |
#if defined( ATMEGA_USART3 )
|
|
|
1237 |
|
|
|
1238 |
ISR(UART3_RECEIVE_INTERRUPT)
|
|
|
1239 |
/*************************************************************************
|
|
|
1240 |
Function: UART3 Receive Complete interrupt
|
|
|
1241 |
Purpose: called when the UART3 has received a character
|
|
|
1242 |
**************************************************************************/
|
|
|
1243 |
{
|
|
|
1244 |
uint16_t tmphead;
|
|
|
1245 |
uint8_t data;
|
|
|
1246 |
uint8_t usr;
|
|
|
1247 |
uint8_t lastRxError;
|
|
|
1248 |
|
|
|
1249 |
|
|
|
1250 |
/* read UART status register and UART data register */
|
|
|
1251 |
usr = UART3_STATUS;
|
|
|
1252 |
data = UART3_DATA;
|
|
|
1253 |
|
|
|
1254 |
/* */
|
|
|
1255 |
lastRxError = (usr & (_BV(FE3)|_BV(DOR3)) );
|
|
|
1256 |
|
|
|
1257 |
/* calculate buffer index */
|
|
|
1258 |
tmphead = ( UART3_RxHead + 1) & UART_RX3_BUFFER_MASK;
|
|
|
1259 |
|
|
|
1260 |
if ( tmphead == UART3_RxTail ) {
|
|
|
1261 |
/* error: receive buffer overflow */
|
|
|
1262 |
lastRxError = UART_BUFFER_OVERFLOW >> 8;
|
|
|
1263 |
} else {
|
|
|
1264 |
/* store new index */
|
|
|
1265 |
UART3_RxHead = tmphead;
|
|
|
1266 |
/* store received data in buffer */
|
|
|
1267 |
UART3_RxBuf[tmphead] = data;
|
|
|
1268 |
}
|
|
|
1269 |
UART3_LastRxError = lastRxError;
|
|
|
1270 |
}
|
|
|
1271 |
|
|
|
1272 |
|
|
|
1273 |
ISR(UART3_TRANSMIT_INTERRUPT)
|
|
|
1274 |
/*************************************************************************
|
|
|
1275 |
Function: UART3 Data Register Empty interrupt
|
|
|
1276 |
Purpose: called when the UART3 is ready to transmit the next byte
|
|
|
1277 |
**************************************************************************/
|
|
|
1278 |
{
|
|
|
1279 |
uint16_t tmptail;
|
|
|
1280 |
|
|
|
1281 |
|
|
|
1282 |
if ( UART3_TxHead != UART3_TxTail) {
|
|
|
1283 |
/* calculate and store new buffer index */
|
|
|
1284 |
tmptail = (UART3_TxTail + 1) & UART_TX3_BUFFER_MASK;
|
|
|
1285 |
UART3_TxTail = tmptail;
|
|
|
1286 |
/* get one byte from buffer and write it to UART */
|
|
|
1287 |
UART3_DATA = UART3_TxBuf[tmptail]; /* start transmission */
|
|
|
1288 |
} else {
|
|
|
1289 |
/* tx buffer empty, disable UDRE interrupt */
|
|
|
1290 |
UART3_CONTROL &= ~_BV(UART3_UDRIE);
|
|
|
1291 |
}
|
|
|
1292 |
}
|
|
|
1293 |
|
|
|
1294 |
|
|
|
1295 |
/*************************************************************************
|
|
|
1296 |
Function: uart3_init()
|
|
|
1297 |
Purpose: initialize UART3 and set baudrate
|
|
|
1298 |
Input: baudrate using macro UART_BAUD_SELECT()
|
|
|
1299 |
Returns: none
|
|
|
1300 |
**************************************************************************/
|
|
|
1301 |
void uart3_init(uint16_t baudrate)
|
|
|
1302 |
{
|
|
|
1303 |
UART3_TxHead = 0;
|
|
|
1304 |
UART3_TxTail = 0;
|
|
|
1305 |
UART3_RxHead = 0;
|
|
|
1306 |
UART3_RxTail = 0;
|
|
|
1307 |
|
|
|
1308 |
/* Set baud rate */
|
|
|
1309 |
if ( baudrate & 0x8000 ) {
|
|
|
1310 |
UART3_STATUS = (1<<U2X3); //Enable 2x speed
|
|
|
1311 |
baudrate &= ~0x8000;
|
|
|
1312 |
}
|
|
|
1313 |
UBRR3H = (uint8_t)(baudrate>>8);
|
|
|
1314 |
UBRR3L = (uint8_t) baudrate;
|
|
|
1315 |
|
|
|
1316 |
/* Enable USART receiver and transmitter and receive complete interrupt */
|
|
|
1317 |
UART3_CONTROL = _BV(RXCIE3)|(1<<RXEN3)|(1<<TXEN3);
|
|
|
1318 |
|
|
|
1319 |
/* Set frame format: asynchronous, 8data, no parity, 1stop bit */
|
|
|
1320 |
#ifdef URSEL3
|
|
|
1321 |
UCSR3C = (1<<URSEL3)|(3<<UCSZ30);
|
|
|
1322 |
#else
|
|
|
1323 |
UCSR3C = (3<<UCSZ30);
|
|
|
1324 |
#endif
|
|
|
1325 |
} /* uart_init */
|
|
|
1326 |
|
|
|
1327 |
|
|
|
1328 |
/*************************************************************************
|
|
|
1329 |
Function: uart3_getc()
|
|
|
1330 |
Purpose: return byte from ringbuffer
|
|
|
1331 |
Returns: lower byte: received byte from ringbuffer
|
|
|
1332 |
higher byte: last receive error
|
|
|
1333 |
**************************************************************************/
|
|
|
1334 |
uint16_t uart3_getc(void)
|
|
|
1335 |
{
|
|
|
1336 |
uint16_t tmptail;
|
|
|
1337 |
uint8_t data;
|
|
|
1338 |
|
|
|
1339 |
if ( UART3_RxHead == UART3_RxTail ) {
|
|
|
1340 |
return UART_NO_DATA; /* no data available */
|
|
|
1341 |
}
|
|
|
1342 |
|
|
|
1343 |
/* calculate /store buffer index */
|
|
|
1344 |
tmptail = (UART3_RxTail + 1) & UART_RX3_BUFFER_MASK;
|
|
|
1345 |
UART3_RxTail = tmptail;
|
|
|
1346 |
|
|
|
1347 |
/* get data from receive buffer */
|
|
|
1348 |
data = UART3_RxBuf[tmptail];
|
|
|
1349 |
|
|
|
1350 |
return (UART3_LastRxError << 8) + data;
|
|
|
1351 |
|
|
|
1352 |
} /* uart3_getc */
|
|
|
1353 |
|
|
|
1354 |
/*************************************************************************
|
|
|
1355 |
Function: uart3_peek()
|
|
|
1356 |
Purpose: Returns the next byte (character) of incoming UART data without
|
|
|
1357 |
removing it from the ring buffer. That is, successive calls to
|
|
|
1358 |
uartN_peek() will return the same character, as will the next
|
|
|
1359 |
call to uartN_getc()
|
|
|
1360 |
Returns: lower byte: next byte in ring buffer
|
|
|
1361 |
higher byte: last receive error
|
|
|
1362 |
**************************************************************************/
|
|
|
1363 |
uint16_t uart3_peek(void)
|
|
|
1364 |
{
|
|
|
1365 |
uint16_t tmptail;
|
|
|
1366 |
uint8_t data;
|
|
|
1367 |
|
|
|
1368 |
if ( UART3_RxHead == UART3_RxTail ) {
|
|
|
1369 |
return UART_NO_DATA; /* no data available */
|
|
|
1370 |
}
|
|
|
1371 |
|
|
|
1372 |
tmptail = (UART3_RxTail + 1) & UART_RX3_BUFFER_MASK;
|
|
|
1373 |
|
|
|
1374 |
/* get data from receive buffer */
|
|
|
1375 |
data = UART3_RxBuf[tmptail];
|
|
|
1376 |
|
|
|
1377 |
return (UART3_LastRxError << 8) + data;
|
|
|
1378 |
|
|
|
1379 |
} /* uart3_peek */
|
|
|
1380 |
|
|
|
1381 |
/*************************************************************************
|
|
|
1382 |
Function: uart3_putc()
|
|
|
1383 |
Purpose: write byte to ringbuffer for transmitting via UART
|
|
|
1384 |
Input: byte to be transmitted
|
|
|
1385 |
Returns: none
|
|
|
1386 |
**************************************************************************/
|
|
|
1387 |
void uart3_putc(uint8_t data)
|
|
|
1388 |
{
|
|
|
1389 |
uint16_t tmphead;
|
|
|
1390 |
|
|
|
1391 |
|
|
|
1392 |
tmphead = (UART3_TxHead + 1) & UART_TX3_BUFFER_MASK;
|
|
|
1393 |
|
|
|
1394 |
while ( tmphead == UART3_TxTail ) {
|
|
|
1395 |
;/* wait for free space in buffer */
|
|
|
1396 |
}
|
|
|
1397 |
|
|
|
1398 |
UART3_TxBuf[tmphead] = data;
|
|
|
1399 |
UART3_TxHead = tmphead;
|
|
|
1400 |
|
|
|
1401 |
/* enable UDRE interrupt */
|
|
|
1402 |
UART3_CONTROL |= _BV(UART3_UDRIE);
|
|
|
1403 |
|
|
|
1404 |
} /* uart3_putc */
|
|
|
1405 |
|
|
|
1406 |
|
|
|
1407 |
/*************************************************************************
|
|
|
1408 |
Function: uart3_puts()
|
|
|
1409 |
Purpose: transmit string to UART3
|
|
|
1410 |
Input: string to be transmitted
|
|
|
1411 |
Returns: none
|
|
|
1412 |
**************************************************************************/
|
|
|
1413 |
void uart3_puts(const char *s )
|
|
|
1414 |
{
|
|
|
1415 |
while (*s) {
|
|
|
1416 |
uart3_putc(*s++);
|
|
|
1417 |
}
|
|
|
1418 |
|
|
|
1419 |
} /* uart3_puts */
|
|
|
1420 |
|
|
|
1421 |
|
|
|
1422 |
/*************************************************************************
|
|
|
1423 |
Function: uart3_puts_p()
|
|
|
1424 |
Purpose: transmit string from program memory to UART3
|
|
|
1425 |
Input: program memory string to be transmitted
|
|
|
1426 |
Returns: none
|
|
|
1427 |
**************************************************************************/
|
|
|
1428 |
void uart3_puts_p(const char *progmem_s )
|
|
|
1429 |
{
|
|
|
1430 |
register char c;
|
|
|
1431 |
|
|
|
1432 |
while ( (c = pgm_read_byte(progmem_s++)) ) {
|
|
|
1433 |
uart3_putc(c);
|
|
|
1434 |
}
|
|
|
1435 |
|
|
|
1436 |
} /* uart3_puts_p */
|
|
|
1437 |
|
|
|
1438 |
|
|
|
1439 |
|
|
|
1440 |
/*************************************************************************
|
|
|
1441 |
Function: uart3_available()
|
|
|
1442 |
Purpose: Determine the number of bytes waiting in the receive buffer
|
|
|
1443 |
Input: None
|
|
|
1444 |
Returns: Integer number of bytes in the receive buffer
|
|
|
1445 |
**************************************************************************/
|
|
|
1446 |
int uart3_available(void)
|
|
|
1447 |
{
|
|
|
1448 |
return (UART_RX3_BUFFER_MASK + UART3_RxHead - UART3_RxTail) % UART_RX3_BUFFER_MASK;
|
|
|
1449 |
} /* uart3_available */
|
|
|
1450 |
|
|
|
1451 |
|
|
|
1452 |
|
|
|
1453 |
/*************************************************************************
|
|
|
1454 |
Function: uart3_flush()
|
|
|
1455 |
Purpose: Flush bytes waiting the receive buffer. Acutally ignores them.
|
|
|
1456 |
Input: None
|
|
|
1457 |
Returns: None
|
|
|
1458 |
**************************************************************************/
|
|
|
1459 |
void uart3_flush(void)
|
|
|
1460 |
{
|
|
|
1461 |
UART3_RxHead = UART3_RxTail;
|
|
|
1462 |
} /* uart3_flush */
|
|
|
1463 |
|
|
|
1464 |
#endif
|
|
|
1465 |
|
|
|
1466 |
#endif /* defined( USART3_ENABLED ) */
|